Large capacity memory systems commonly employ error correction techniques to improve the yield and reliability of the multitude of memory bits in a memory. One technique for error correction includes the use of Error Correction Code (ECC), which uses addition memory bits to represent an attribute of a memory word that the additional bits are associated with. For example, the additional bits could represent the parity of a word or even replicate the entire word itself. A variety of ECC methodologies exist to strike a balance between the physical overhead associated with additional memory bits, the impact on READ latency required to evaluate whether a memory word has a failure and the efficacy of the ECC to correct the memory word it is associated with.
With geometric scaling of memories and the increased use of multi-level bit (MLB) storage to represent more than one logical state per bit, memories must rely on the detection of fewer electrons to detect a stored memory state. With increased demands for wider operating temperature range memory reliability is further challenged. In particular with NAND Flash non-volatile memories, an increase in the required Program/Erase cycles further limits the reliability of advanced memory systems.